module Counter2b(clk, reset, hold, out);
input clk;
input reset;
input hold;
output reg [1:0] out;

always @(posedge clk) begin
	if(hold) begin
		out = out;
	end else if(!reset) begin
		out = 0;
	end else begin
		out = out + 1;
	end
end


endmodule